The present invention relates generally to memory devices, and, more particularly, to a system for redundancy management in a memory device.
Conventional memory devices including static random access memory (SRAM) devices include multiple memory cells arranged as memory input/outputs (I/Os). Each memory I/O has an array logic circuit and a corresponding periphery logic circuit that enables an external device, such as a microprocessor, to access the array logic circuit for reading and writing data. The periphery logic circuit includes read and write latches (among other elements) to read and write data bits to the memory array. Additionally, the memory device includes redundant memory cells arranged as redundant memory I/Os. Similar to the memory I/O, each redundant memory I/O has a corresponding redundant periphery logic circuit that functions similar to the periphery logic circuit. The redundant memory arrays and the redundant periphery logic circuit replace the memory I/O if a defect is detected in the memory I/O. A built-in self-test (BIST) circuitperforms a BIST operation on the memory device to identify defective memory I/Os. Upon completion of the BIST operation, an acknowledgment signal is generated and decoded by redundancy decoders to identify and replace the defective memory array and corresponding periphery logic circuit with a functional redundant memory array and corresponding redundant periphery logic circuit.
When data bits are received by the memory device for storing in the defective memory array, the memory device shifts the data bits and stores them in the substitute redundant memory array. The data bits are shifted from the periphery logic circuit associated with the defective memory array by way of one or more periphery logic circuits associated with one or more memory arrays until they are received by the redundant periphery logic circuit and stored in the redundant memory array.
Though existing memory devices have built-in systems to switch off the defective memory I/O, circuits associated with the periphery logic circuit remain powered up and continue consuming leakage power. Further, the redundant memory array and corresponding redundant periphery logic circuit also are powered when not in use. The combined power consumption of the periphery logic circuit of the defective memory I/O and the unused redundant memory array and redundant periphery logic circuit contributes to a substantial portion of the power budget of memory devices, which is particularly critical in nanometer, low-power-process technologies.
Therefore, it would be advantageous to have a system for managing redundancy in a memory device that reduces the leakage power, reduces the power budget of the memory device, and overcomes the above-mentioned limitations of conventional redundancy management systems.